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RT8876A ? ds8876a-02 october 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dual channel pwm controller with 3/2/1 phase for core vr and single phase for axg vr general description the RT8876A is a vr12/imvp7 compliant cpu power controller which includes two channels : a 3/2/1 phase with 3 integrated drivers synchronous buck controller for the core vr, and a single phase buck controller for the axg vr. the RT8876A adopts g-navp tm (green native adaptive voltage positioning), which is richtek's proprietary topology derived from a finite dc gain compensator with current mode control, making it an easy setting pwm controller, meeting all intel cpu requirements of avp. based on the g-navp tm topology, the RT8876A also features a quick response mechanism for optimizing avp performance during load transient. the RT8876A supports mode transition function with various operating states. a serial vid (svid) interface is built in the RT8876A to communicate with intel vr12/imvp7 compliant cpu. the RT8876A supports vid on-the-fly function with three different slew rates : fast, slow and decay. by utilizing the g-navp tm topology, the operating frequency of the RT8876A varies with vid, load and input voltage to further enhance the efficiency even in ccm. the built-in high accuracy dac converts the svid code ranging from 0.25v to 1.52v with 5mv per step. the RT8876A integrates a high accuracy adc for platform setting functions, such as no-load offset or over current level. features z z z z z vr12/imvp7 compatible power management z z z z z 3/2/1 phase for core vr and single phase for axg vr z z z z z 3 embedded mosfet drivers at the core vr z z z z z g-navp tm topology z z z z z serial vid interface z z z z z 0.5% dac accuracy z z z z z differential remote voltage sensing z z z z z built-in adc for platform programming z z z z z accurate current balance z z z z z system thermal compensated avp z z z z z diode emulation mode at light load condition for single phase z z z z z fast transient response z z z z z 1.1v initial / 0.0v initial for both rails at startup z z z z z power ready indicator z z z z z thermal throttling z z z z z current monitor output z z z z z ovp, uvp, ocp, otp, uvlo z z z z z external no-load offset setting for both rails z z z z z dvid enhancement z z z z z 56-lead wqfn package z z z z z rohs compliant and halogen free applications z vr12/imvp7 intel core supply z notebook/ desktop computer/ servers multi-phase cpu core supply z avp step-down converter simplified application circuit v core phase3 phase2 phase1 RT8876A pwma vr_rdy vrhot vclk vdio alert to cpu v axg mosfet mosfet mosfet rt9612 mosfet
RT8876A 2 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 qrset multi-phase core vr channel quick response time setting and initial voltage (v initial ) setting. 2 dvida place a resistor and a capacitor from this pin to gnd to enhance dvid performance. short this pin to gnd if not use. 5, 4, 8 isen [1:3] n negative current sense pin of phase 1, 2, 3 for core vr. 6, 3, 7 isen [1:3] p positive current sense pin of phase 1, 2, 3 for core vr. 9 rset multi-phase core vr ramp setting. this is used to set the multi-phase core vr loop external ramp slope. 10 comp multi-phase core vr compensation node. this pin is the output node of the error amplifier. 11 fb multi-phase core vr feedback input. this is the negative input node of the error amplifier. 12 rgnd return ground for multi-phase core vr. this pin is the negative node of the differential remote voltage sensing. 13 dvid place a resistor and a capacitor from this pin to gnd to enhance dvid performance. short this pin to gnd if not use. 14 ofs output voltage offset setting. 15 imon current monitor output. this pin outputs a voltage proportional to the output current. 16 imonfb current monitor output gain external setting. connect this pin with one resistor to cpu v cc_sense while imon pin is connected to ground with one another resistor. the current monitor output gain can be set by the ratio of these two resistors. ordering information note : richtek products are : ` rohs compliant and compatible with the current requirements of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. package type qw : wqfn-56l 7x7 (w-type) RT8876A lead plating system g : green (halogen free and pb free) pin configurations wqfn-56l 7x7 (top view) qrset isen2n isen2p rgnd fb comp rset isen3n isen3p isen1n isen1p dvida imon imonfb vclk vdio ibias ofsa tempmax iccmax iccmaxa imonfba imona tonseta tsena tsen qrseta pwma en vr_rdy vcc5 ocset ocseta ugate2 phase2 lgate2 boot1 ugate1 ugate3 phase1 lgate1 vcc12 lgate3 isenap isenan compa rgnda fba dvid ofs boot3 tonset boot2 phase3 alert 1 2 3 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 17 16 15 42 41 40 39 38 37 36 35 34 33 32 45 46 47 48 49 50 51 52 53 54 55 56 31 30 29 27 28 13 14 44 43 gnd 57 vrhot marking information RT8876Agqw : product number ymdnn : date code RT8876A gqw ymdnn
RT8876A 3 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function 17 vclk synchronous clock from the cpu. 18 vdio controller and cpu data transmission interface. 19 alert svid alert pin. (active low) 20 ibias internal bias current setting. connecting this pin to gnd by a resistor can set the internal current. 21 tempmax adc input for multi-phase core vr maximum temperature setting. 22 iccmax adc input for multi-phase core vr maximum current setting. 23 iccmaxa adc input for single phase axg vr maximum current setting. 24 imonfba single phase axg vr current monitor output gain external setting. connect this pin with one resistor to axg rail v ccaxg_sense while imona pin is connected to ground with another resistor. the current monitor output gain can be set by the ratio of these two resistors. 25 imona single phase axg vr current monitor output. this pin outputs a voltage proportional to the output current. 26 ofsa set the axg no-load offset. 27 rgnda return ground for single phase axg vr. this pin is the negative node of the differential remote voltage sensing. 28 fba single phase axg vr feedback input. this is the negative input node of the error amplifier. 29 compa single phase axg vr compensation node. this pin is the output node of the error amplifier. 30 isenan negative current sense pin for single phase axg vr. 31 isenap positive current sense pin for single phase axg vr. 32 qrseta single phase axg vr quick response time setting and address flipping setting. 33 pwma pwm output for single phase axg vr. 34 en voltage regulator enabler. 35 vr_rdy power ready indicator of multi-phase core vr. 36 vcc5 chip power. connect this pin to gnd by a ceramic cap larger than 1 f. 37 ocseta single phase axg vr over current protection setting. connect a resistor voltage divider from vcc to ground, the joint of the resistor divider is connected to ocseta pin, with a voltage v ocseta , to set the over current threshold i limit_axg . 38 ocset multi-phase core vr over current protection setting. connect a resistor voltage divider from vcc to ground, the joint of the resistor divider is connected to ocset pin, with a voltage v ocset , to set the over current threshold i limit_core . 39 tsena thermal monitor sense point of axg vr. 40 tsen thermal monitor sense point of core vr. 41 vrhot thermal monitor output (active low). 42 tonseta single phase axg vr on-time setting. connect this pin to vin with one resistor to set ripple size in pwm-mode. 43 tonset multi-phase core vr on-time setting. connect this pin to vin with one resistor to set ripple size in pwm-mode. 48 vcc12 driver power. connect this pin to gnd by a ceramic cap larger than 1 f.
RT8876A 4 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram tempmax control & protection logic uvlo svid xcvr adc mux ton gen + - pwm cmp + - soft-start & slew rate control v seta error amp dac from control logic + - to protection logic ocp ovp/uvp/nvp 20 ton gen + - pwm cmp + - soft-start & slew rate control v set dac phase selector + - + v qr_trip qr cmp + - + - + - from control logic to protection logic ocp ovp/uvp/nvp current balance 10 10 10 ocset isen3p isen3n isen2n isen2p isen1p vcc12 isen1n vrhot iccmax compa gnd vdio vclk isenan ocseta lgatex phasex ugatex bootx qrseta qrset isenap pwma en rgnda fb comp tonseta rset tonset rgnd fba alert current monitor v set imonfb imon current monitor imona v seta imonfba offset generator ofs iccmaxa tsena tsen vcc5 vr_rdy sum ibias offset generator ofsa + 1/20 dvida 1/20 dvid + por +/- 3-ph driver pwm [1:3] offset cancellation offset cancellation pin no. pin name pin function 49, 53, 47 lgate [1:3] low side drive output. this pin drives the gate of low side mosfet. 50, 54, 46 phase [1:3] switch node of high side driver. connect the pin to high side mosfet source together with the low side mosfet drain and the inductor. 51, 55, 45 ugate [1:3] high side drive output. connect the pin to the gate of high side mosfet. 52, 56, 44 boot [1:3] bootstrap power pin. this pin powers high side mosfet driver. 57 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8876A 5 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation pwm cmp generate a signal to trigger ton pulse. ton gen generate the pwm1 to pwm4 sequentially according to the phase control signal from the loop control protection logic. control and protection logic execute the command from cpu. the control logic also generates the digital code of the vid. control the power on sequence control the protection behavior. control the operational phase number. current balance generate the signal to control ton to achieve current balance. offset cancellation cancel the current/voltage ripple issue to get the accurate vsen. uvlo detect the dvd and vcc voltage and issue por signal as they are large enough. dac generate a analog signal according to the digital code generated by control logic. soft-start and slew rate control control the dynamic vid slew rate of v set according to the setvid fast or setvid slow. 3-phase driver generate ugate [1:3] and lgate [1:3] signal by pwm [1:3] signal.
RT8876A 6 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 1. vr12 vid code table vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 0 0 0 0 0 0 0 0 0 0.000 0 0 0 0 0 0 0 1 0 1 0.250 0 0 0 0 0 0 1 0 0 2 0.255 0 0 0 0 0 0 1 1 0 3 0.260 0 0 0 0 0 1 0 0 0 4 0.265 0 0 0 0 0 1 0 1 0 5 0.270 0 0 0 0 0 1 1 0 0 6 0.275 0 0 0 0 0 1 1 1 0 7 0.280 0 0 0 0 1 0 0 0 0 8 0.285 0 0 0 0 1 0 0 1 0 9 0.290 0 0 0 0 1 0 1 0 0 a 0.295 0 0 0 0 1 0 1 1 0 b 0.300 0 0 0 0 1 1 0 0 0 c 0.305 0 0 0 0 1 1 0 1 0 d 0.310 0 0 0 0 1 1 1 0 0 e 0.315 0 0 0 0 1 1 1 1 0 f 0.320 0 0 0 1 0 0 0 0 1 0 0.325 0 0 0 1 0 0 0 1 1 1 0.330 0 0 0 1 0 0 1 0 1 2 0.335 0 0 0 1 0 0 1 1 1 3 0.340 0 0 0 1 0 1 0 0 1 4 0.345 0 0 0 1 0 1 0 1 1 5 0.350 0 0 0 1 0 1 1 0 1 6 0.355 0 0 0 1 0 1 1 1 1 7 0.360 0 0 0 1 1 0 0 0 1 8 0.365 0 0 0 1 1 0 0 1 1 9 0.370 0 0 0 1 1 0 1 0 1 a 0.375 0 0 0 1 1 0 1 1 1 b 0.380 0 0 0 1 1 1 0 0 1 c 0.385 0 0 0 1 1 1 0 1 1 d 0.390 0 0 0 1 1 1 1 0 1 e 0.395 0 0 0 1 1 1 1 1 1 f 0.400 0 0 1 0 0 0 0 0 2 0 0.405 0 0 1 0 0 0 0 1 2 1 0.410 0 0 1 0 0 0 1 0 2 2 0.415 0 0 1 0 0 0 1 1 2 3 0.420 0 0 1 0 0 1 0 0 2 4 0.425 0 0 1 0 0 1 0 1 2 5 0.430 0 0 1 0 0 1 1 0 2 6 0.435 0 0 1 0 0 1 1 1 2 7 0.440
RT8876A 7 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 0 1 0 1 0 0 0 2 8 0.445 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 a 0.455 0 0 1 0 1 0 1 1 2 b 0.460 0 0 1 0 1 1 0 0 2 c 0.465 0 0 1 0 1 1 0 1 2 d 0.470 0 0 1 0 1 1 1 0 2 e 0.475 0 0 1 0 1 1 1 1 2 f 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 a 0.535 0 0 1 1 1 0 1 1 3 b 0.540 0 0 1 1 1 1 0 0 3 c 0.545 0 0 1 1 1 1 0 1 3 d 0.550 0 0 1 1 1 1 1 0 3 e 0.555 0 0 1 1 1 1 1 1 3 f 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590 0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 a 0.615 0 1 0 0 1 0 1 1 4 b 0.620 0 1 0 0 1 1 0 0 4 c 0.625 0 1 0 0 1 1 0 1 4 d 0.630 0 1 0 0 1 1 1 0 4 e 0.635 0 1 0 0 1 1 1 1 4 f 0.640 0 1 0 1 0 0 0 0 5 0 0.645
RT8876A 8 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 a 0.695 0 1 0 1 1 0 1 1 5 b 0.700 0 1 0 1 1 1 0 0 5 c 0.705 0 1 0 1 1 1 0 1 5 d 0.710 0 1 0 1 1 1 1 0 5 e 0.715 0 1 0 1 1 1 1 1 5 f 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770 0 1 1 0 1 0 1 0 6 a 0.775 0 1 1 0 1 0 1 1 6 b 0.780 0 1 1 0 1 1 0 0 6 c 0.785 0 1 1 0 1 1 0 1 6 d 0.790 0 1 1 0 1 1 1 0 6 e 0.795 0 1 1 0 1 1 1 1 6 f 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850
RT8876A 9 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 1 1 1 1 0 1 0 7 a 0.855 0 1 1 1 1 0 1 1 7 b 0.860 0 1 1 1 1 1 0 0 7 c 0.865 0 1 1 1 1 1 0 1 7 d 0.870 0 1 1 1 1 1 1 0 7 e 0.875 0 1 1 1 1 1 1 1 7 f 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 a 0.935 1 0 0 0 1 0 1 1 8 b 0.940 1 0 0 0 1 1 0 0 8 c 0.945 1 0 0 0 1 1 0 1 8 d 0.950 1 0 0 0 1 1 1 0 8 e 0.955 1 0 0 0 1 1 1 1 8 f 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 a 1.015 1 0 0 1 1 0 1 1 9 b 1.020 1 0 0 1 1 1 0 0 9 c 1.025 1 0 0 1 1 1 0 1 9 d 1.030 1 0 0 1 1 1 1 0 9 e 1.035 1 0 0 1 1 1 1 1 9 f 1.040 1 0 1 0 0 0 0 0 a 0 1.045 1 0 1 0 0 0 0 1 a 1 1.050 1 0 1 0 0 0 1 0 a 2 1.055
RT8876A 10 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 1 0 1 0 0 0 1 1 a 3 1.060 1 0 1 0 0 1 0 0 a 4 1.065 1 0 1 0 0 1 0 1 a 5 1.070 1 0 1 0 0 1 1 0 a 6 1.075 1 0 1 0 0 1 1 1 a 7 1.080 1 0 1 0 1 0 0 0 a 8 1.085 1 0 1 0 1 0 0 1 a 9 1.090 1 0 1 0 1 0 1 0 a a 1.095 1 0 1 0 1 0 1 1 a b 1.100 1 0 1 0 1 1 0 0 a c 1.105 1 0 1 0 1 1 0 1 a d 1.110 1 0 1 0 1 1 1 0 a e 1.115 1 0 1 0 1 1 1 1 a f 1.120 1 0 1 1 0 0 0 0 b 0 1.125 1 0 1 1 0 0 0 1 b 1 1.130 1 0 1 1 0 0 1 0 b 2 1.135 1 0 1 1 0 0 1 1 b 3 1.140 1 0 1 1 0 1 0 0 b 4 1.145 1 0 1 1 0 1 0 1 b 5 1.150 1 0 1 1 0 1 1 0 b 6 1.155 1 0 1 1 0 1 1 1 b 7 1.160 1 0 1 1 1 0 0 0 b 8 1.165 1 0 1 1 1 0 0 1 b 9 1.170 1 0 1 1 1 0 1 0 b a 1.175 1 0 1 1 1 0 1 1 b b 1.180 1 0 1 1 1 1 0 0 b c 1.185 1 0 1 1 1 1 0 1 b d 1.190 1 0 1 1 1 1 1 0 b e 1.195 1 0 1 1 1 1 1 1 b f 1.200 1 1 0 0 0 0 0 0 c 0 1.205 1 1 0 0 0 0 0 1 c 1 1.210 1 1 0 0 0 0 1 0 c 2 1.215 1 1 0 0 0 0 1 1 c 3 1.220 1 1 0 0 0 1 0 0 c 4 1.225 1 1 0 0 0 1 0 1 c 5 1.230 1 1 0 0 0 1 1 0 c 6 1.235 1 1 0 0 0 1 1 1 c 7 1.240 1 1 0 0 1 0 0 0 c 8 1.245 1 1 0 0 1 0 0 1 c 9 1.250 1 1 0 0 1 0 1 0 c a 1.255 1 1 0 0 1 0 1 1 c b 1.260
RT8876A 11 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 1 1 0 0 1 1 0 0 c c 1.265 1 1 0 0 1 1 0 1 c d 1.270 1 1 0 0 1 1 1 0 c e 1.275 1 1 0 0 1 1 1 1 c f 1.280 1 1 0 1 0 0 0 0 d 0 1.285 1 1 0 1 0 0 0 1 d 1 1.290 1 1 0 1 0 0 1 0 d 2 1.295 1 1 0 1 0 0 1 1 d 3 1.300 1 1 0 1 0 1 0 0 d 4 1.305 1 1 0 1 0 1 0 1 d 5 1.310 1 1 0 1 0 1 1 0 d 6 1.315 1 1 0 1 0 1 1 1 d 7 1.320 1 1 0 1 1 0 0 0 d 8 1.325 1 1 0 1 1 0 0 1 d 9 1.330 1 1 0 1 1 0 1 0 d a 1.335 1 1 0 1 1 0 1 1 d b 1.340 1 1 0 1 1 1 0 0 d c 1.345 1 1 0 1 1 1 0 1 d d 1.350 1 1 0 1 1 1 1 0 d e 1.355 1 1 0 1 1 1 1 1 d f 1.360 1 1 1 0 0 0 0 0 e 0 1.365 1 1 1 0 0 0 0 1 e 1 1.370 1 1 1 0 0 0 1 0 e 2 1.375 1 1 1 0 0 0 1 1 e 3 1.380 1 1 1 0 0 1 0 0 e 4 1.385 1 1 1 0 0 1 0 1 e 5 1.390 1 1 1 0 0 1 1 0 e 6 1.395 1 1 1 0 0 1 1 1 e 7 1.400 1 1 1 0 1 0 0 0 e 8 1.405 1 1 1 0 1 0 0 1 e 9 1.410 1 1 1 0 1 0 1 0 e a 1.415 1 1 1 0 1 0 1 1 e b 1.420 1 1 1 0 1 1 0 0 e c 1.425 1 1 1 0 1 1 0 1 e d 1.430 1 1 1 0 1 1 1 0 e e 1.435 1 1 1 0 1 1 1 1 e f 1.440 1 1 1 1 0 0 0 0 f 0 1.445 1 1 1 1 0 0 0 1 f 1 1.450 1 1 1 1 0 0 1 0 f 2 1.455 1 1 1 1 0 0 1 1 f 3 1.460 1 1 1 1 0 1 0 0 f 4 1.465
RT8876A 12 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 1 1 1 1 0 1 0 1 f 5 1.470 1 1 1 1 0 1 1 0 f 6 1.475 1 1 1 1 0 1 1 1 f 7 1.480 1 1 1 1 1 0 0 0 f 8 1.485 1 1 1 1 1 0 0 1 f 9 1.490 1 1 1 1 1 0 1 0 f a 1.495 1 1 1 1 1 0 1 1 f b 1.500 1 1 1 1 1 1 0 0 f c 1.505 1 1 1 1 1 1 0 1 f d 1.510 1 1 1 1 1 1 1 0 f e 1.515 1 1 1 1 1 1 1 1 f f 1.520
RT8876A 13 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. serial vid command code commands master payload contents slave payload contents description 00h not supported n/a n/a n/a 01h setvid_fast vid code n/a set new target vid code, vr jumps to new vid target with controlled default ?fast? slew rate 12.5mv/ s. 02h setvid_slow vid code n/a set new target vid code, vr jumps to new vid target with controlled default ?slow? slew rate 3.125mv/ s. 03h setvid_decay vid code n/a set new target vid code, vr jumps to new vid target, but does not control the slew rate. the output voltage decays at a rate proportional to the load current 04h setps byte indicating power states n/a set power state 05h setregadr pointer of registers in data table n/a set the pointer of the data register 06h setregdat new data register content n/a write the contents to the data register 07h getreg pointer of registers in data table specified register contents slave returns the contents of the specified register as the payload. 08h - 1fh not supported n/a n/a n/a
RT8876A 14 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 3. svid data and configuration register index register name description access default 00h vendor_id vendor id ro 1eh 01h product_id product id ro 5bh 02h product_revision product revision ro 01h 05h protocol_version svid protocol version ro 01h 06h vr_capability bit mapped register, identifies the svid vr capabilities and which of the optional telemetry registers is supported. ro 81h 10h status_1 data register containing the status of vr r-m, w-pwm 00h 11h status_2 data register containing the status of transmission. r-m, w-pwm 00h 12h temperature_zone data register showing temperature zone that has been entered. r-m, w-pwm 00h 15h output_current data register showing direct adc conversion of output current, scaled to icc_max = adc full range. binary format (ie : 64h = 100/255 icc_max) r-m, w-pwm 00h 1ch status_2_lastread the register contains a copy of the status_2 r-m, w-pwm 00h 21h icc_max data register containing the maximum icc the platform supports. binary format in a. (ie : 64h = 100a) ro, platform n/a 22h temp_max data register containing the maximum temperature the platform supports. binary format in c. (ie : 64h = 100 c) not supported by axg vr. ro, platform n/a 24h sr_fast data register containing the capability of fast slew rate the platform can sustain. binary format in mv/ s. (ie : 0ah = 10mv/ s) ro 0ah 25h sr_slow data register containing the capability of slow slew rate. binary format in mv/ s. (ie : 02h = 2mv/ s) ro 02h 30h vout_max the register is programmed by the master and sets the maximum vid. rw, master fbh 31h vid_setting data register containing currently programmed vid rw, master 00h 32h power_state register containing the current programmed power state rw, master 00h 33h offset set offset in vid steps rw, master 00h 34h multi_vr_config bit mapped data register which configures multiple vrs? behavior on the same bus rw, master 00h 35h pointer scratch pad register for temporary storage of the setregadr pointer register rw, master 30h notes : ro = read only rw = read/write r-m = read by master w-pwm = write by pwm only platform = programmed by platform master = programmed by the master pwm = programmed by the vr control ic
RT8876A 15 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended operating conditions (note 4) z supply voltage, vcc12 ------------------------------------------------------------------------- --- 4.5v to 13.2v z supply voltage, vcc5 ----------------------------------------------------------------------------- 4.5v to 5.5v z input voltage, (v in + vcc12) --------------------------------------------------------------------- <35v z junction temperature range -- -------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -- -------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vcc12 to gnd --------------------------------------------------------------------------------------- ? 0.3v to 15v z vcc5 to gnd ---------------------------------------------------------------------------------------- ? 0.3v to 6.5v z rgnd, rgnda to gnd ---------------------------------------------------------------------------- ? 0.3v to 0.3v z tonset, tonseta to gnd -- -------------------------------------------------------------------- ? 0.3v to 28v z bootx to phasex --------------------------------------------------------------------------------- ? 0.3v to 15v z phasex to gnd dc ------------------------------------------------------------------------------------------------------- ? 0.3v to 30v <20ns -------------------------------------------------------------------------------------------------- ? 10v to 35v z lgatex to gnd dc ------------------------------------------------------------------------------------------------------- (gnd ? 0.3v) to (vcc12 + 0.3v) <20ns -------------------------------------------------------------------------------------------------- (gnd ? 2v) to (vcc12 + 0.3v) z ugatex to gnd dc ------------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) <20ns -------------------------------------------------------------------------------------------------- (v phase ? 2v) to (v boot + 0.3v) z pwma to gnd --------------------------------------------------------------------------------------- ? 0.3v to 7v z other pins --------------------------------------------------------------------------------------------- ? 0.3v to (vcc5 + 0.3v) z power dissipation, p d @ t a = 25 c wqfn ? 56l 7x7 -------------------------------------------------------------------------------------- 3.226w z package thermal resistance (note 2) wqfn ? 56l 7x7, ja -------------------------------------------------------------------------------- 31 c/w wqfn ? 56l 7x7, jc ------------------------------------------------------------------------------- 6 c/w z junction temperature ------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------- 260 c z storage temperature range -- -------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ----------------- ------------------------------------------------------- 2kv
RT8876A 16 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit supply input vcc12 supply voltage v cc12 4.5 -- 13.2 v vcc5 supply voltage v cc5 4.5 5 5.5 v vcc12 supply current i vcc12 v cc12 = 12v, v bootx = 12v -- 1.2 -- ma vcc5 supply current i vcc5 en = 1.05v, not switching -- 12 20 ma shutdown current i shdn en = 0v -- -- 5 a power on reset (por) por threshold v por_r v cc12 rising 3 -- 4.4 v por hysteresis v por_hys -- 0.5 -- v reference and dac v dac = 1.000 to 1.520 (no load, active mode) ? 0.5 0 0.5 %vid v dac = 0.800 to 1.000 ? 5 0 5 v dac = 0.500 to 0.800 ? 8 0 8 dc accuracy v dac = 0.250 to 0.500 ? 8 0 8 mv rgnd current rgnd current i rgnd en = 1.05v, not switching -- -- 500 a slew rate setvid slow 2.5 3.125 3.75 mv/ s dynamic vid slew rate setvid fast 10 12.5 15 mv/ s error amplifier dc gain r l = 47k 70 80 -- db gain-bandwidth product gbw c load = 5pf -- 10 -- mhz slew rate sr c load = 10pf (gain = ? 4, r f = 47k, v out = 0.5v ? 3v) -- 5 -- v/ s output voltage range v comp r l = 47k 0.3 -- 3.6 v max source/sink current i outea v comp = 2v -- 250 -- a current sense amplifier input offset voltage v oscs ? 0.75 -- 0.75 mv impedance at neg. input r isenxn 1 -- -- m impedance at pos. input r isenxp 1 -- -- m core vr -- 10 -- v/v dc gain axg vr -- 20 -- v/v input range v isen_in ? 50 -- 100 mv v isen linearity v isen _acc ? 30mv < v isen_in < 50mv ? 1 -- 1 % ton setting tonset/tonseta pin voltage v to n i rton = 80 a, v dac = 0.75v -- 0.75 -- v ccm on-time setting t on i rton = 80 a, ps0, ps1 275 305 335 ns electrical characteristics (v cc5 = 5v, v cc12 = 12v, t a = 25 c, unless otherwise specified)
RT8876A 17 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit tonset/tonseta input current range i rton 25 -- 280 a ton in ps2 (core only) t on ps2 with respect to ps0 ton -- 85 -- % minimum off-time t off_min -- 250 -- ns ibias ibias pin voltage v ibias r ibias = 53.6k 2.09 2.14 2.19 v qrset/qrseta quick response tonx t onx _qr v dac = 0.75v, q rset = 1.2v, i rton = 80 a -- 305 -- ns qrset source current i qrset before por -- 80 -- a v ih v cc5 ? 0.5 -- -- v v initial threshold v il -- -- v cc5 ? 1.8 v v ih v cc5 ? 0.5 -- -- v non-flipping addr threshold v il -- -- v cc5 ? 1.8 v ofs/ofsa function ofs enable/disable threshold voltage v en_ofs v ofs > v en_ofs before en rising 0.52 1.2 -- v v id = 1v, offset +400mv 1.58 1.6 1.62 v id = 1v, offset ? 200mv 0.98 1 1.02 set ofs/ofsa voltage v id = 1v. no offset voltage 1.19 1.2 1.21 v impedance r ofs 1 -- -- m rset setting rset voltage v rset v dac = 1v -- 1.000 -- v zero current detection zero current detection threshold v zcd isen1p ? isen1n, isenap ? isenan -- 1 -- mv protection under voltage lockout (uvlo) threshold v uvlo falling edge, 100mv hysteresis 4.04 4.24 4.44 v absolute over voltage protection threshold v ovabs with respect to v out(max) , pin offset is disabled 100 150 200 mv delay of uvlo t uvlo rising above threshold -- 3 -- s delay of ovp t ov isen1n/isenan rising above threshold -- 1 -- s under voltage protection (uvp) threshold v uv measured at isen1n/isenan with respect to unloaded output voltage (uov) (for 0.8v < uov < 1.52v) ? 350 ? 300 ? 250 mv delay of uvp t uv isen1n/isenan falling below threshold -- 3 -- s negative voltage protection threshold v nv ? 100 ? 50 -- mv
RT8876A 18 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit delay of nvp t nv isen1n/isenan falling below threshold -- 1 -- s g ilimt = v ocset / (v isenxp ? v isenxn ) v ocset = 2.4v, (v isenxp ? v isenxn ) = 50mv 43.2 48 52.8 current limit threshold voltage (per phase) g ilimt = v ocseta / (v isen ap ? v isenan ) v ocseta = 2.4v, (v isenap ? v isenan ) = 25mv 86.4 96 105.6 v/v current limit latch counter (per phase) n ilimit continuous current limit cycle -- 15 -- times logic inputs v ih_en 0.7 -- -- en threshold voltage v il_en -- -- 0.3 v en hysteresis v enhys -- 30 -- mv leakage current of en i en ? 1 -- 1 a v ih 0.665 -- -- vclk, vdio threshold vo lta g e v il -- -- 0.367 v vclk, vdio hysteresis v hys -- 70 -- mv leakage current of vclk, vdio i leak_in ? 1 -- 1 a alert alert low voltage v alert i alert = 4ma -- -- 0.4 v power on sequence svid ready delay time t a from en to vr controller is ready to accept svid command -- -- 2 ms vr ready trip threshold v th_vr_rdy isen1n ? 1 st v dac -- ? 100 -- mv vr_rdy low voltage v vr_rdy i vr_rdy = 4ma -- -- 0.4 v vr_rdy delay t vr_rdy isen1n = v initial to vr_rdy hi gh -- 100 -- s thermal throttling vrhot output voltage v vrhot i vrhot = 40ma -- -- 0.4 v current monitor current monitor maximum output voltage in operating range v imon v dac = 1v, v rimonfb = 100mv, r imonfb = 10k , r imon = 330k 3.2 3.3 3.4 v high impedance output leakage current of alert, vr_rdy and vrhot pins i leak_out ? 1 -- 1 a svid svid frequency f svidfreq 5 25 26.25 mhz svid clock to data delay t co 4 -- 8.3 ns setup time of vdio t su 7 -- -- ns hold time of vdio t hld 14 -- -- ns
RT8876A 19 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit adc c iccmax1 v iccmax = 12.74% x vcc5 29 32 35 c iccmax2 v iccmax = 25.284% x vcc5 61 64 67 digital code of iccmax c iccmax3 v iccmax = 50.372% x vcc5 125 128 131 decimal c iccmaxa1 v iccmaxa = 3.332% x vcc5 5 8 11 c iccmaxa2 v iccmaxa = 6.468% x vcc5 13 16 19 digital code of iccmaxa c iccmaxa3 v iccmaxa = 12.74% x vcc5 29 32 35 decimal c tempmax1 v temp max = 33.516% x vcc5 82 85 88 c tempmax2 v temp max = 39.396% x vcc5 97 100 103 digital code of tempmax c tempmax3 v temp max = 49.196% x vcc5 122 125 128 decimal c ocr1 v imona = v imona = 3.3v 252 255 255 c ocr2 v imona = v imona = 2.208v 167 170 173 digital code of output current report c ocr3 v imona = v imona = 1.107v 82 85 88 decimal updating period of output current report t ocr -- -- 500 s tolerance band of temp. zone trip points b7, b6, b5 t tsen_tol 20 -- 20 mv updating period of temperature zone t tz -- -- 500 s timing ugate rise time t ugater 3nf load -- 25 -- ns ugate fall time t ugatef 3nf load -- 12 -- ns lgate rise time t lgater 3nf load -- 24 -- ns lgate fall time t lgatef 3nf load -- 10 -- ns t ugatepgh -- 60 -- t ugatepdl -- 22 -- t lgatepdh -- 20 -- propagation delay t lgatepdl -- 8 -- ns output ugate drive source current i ugatesr v bootx ? v phasex = 12v, v ugatex ? v phasex = 2v -- 2 -- a ugate drive sink resistance r ugatesk v bootx ? v phasex = 12v -- 1.4 -- lgate drive source current i lgatesr v lgatex = 2v -- 2.2 -- a lgate drive sink resistance r lgatesk -- 1.1 -- ugate drive source i ugatesr v bootx ? v phasex = 12v, v ugatex ? v phasex = 2v -- 2 -- a dvid, dvida, iccmax, iccmaxa and tempmax current sourcing out from dvidx pin to gnd i dvidx during dynamic vid fast event 6 8 10 a
RT8876A 20 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit current sinking in from 5v to iccmax pin i ccmax after en -- 16 -- a current sinking in from 5v to iccmaxa pin i ccmaxa after en -- 128 -- a current sinking in from 5v to tempmax pin i tempmax after en -- 16 -- a
RT8876A 21 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit r t 8 8 7 6 a 1 2 v 12v 5v isenan isenap vcc5 pwma en fba compa imonfba imonfb 34 33 16 29 28 24 36 31 30 tonseta tonset 43 42 ofsa 1 qrseta iccmaxa 23 32 v c c 5 iccmax tempmax 21 22 gnd 57 (exposed pad) rset 9 dvid 13 v ccaxg_sense r n t c v c c _ s e n s e comp 10 fb 11 ocseta 37 vcc5 ocset 38 vcc5 26 chip enable qrset r ntc rgnda 27 ofs 14 v in v in dvida 2 vr_rdy 41 35 vdio vclk alert 17 18 19 vr_rdy vdio vclk alert vccio vrhot vrhot rt9612 vcc pwm boot ugate phase lgate pgnd tsen 40 r n t c vcc5 vcc12 48 12v isen1n isen1p lgate1 5 6 49 v i n phase1 50 ugate1 51 boot1 52 isen3n isen3p lgate3 8 7 47 v i n phase3 46 ugate3 45 boot3 44 isen2n isen2p lgate2 4 3 53 v in phase2 54 ugate2 55 boot2 56 v ssaxg_sense v out_axg v ss_sense load v out_core rgnd 12 tsena 39 r n t c vcc5 ibias 20 imon 15 imona 25 load 1 0 0 1 0 0 figure 1. thernal compersation at voltage loop for axg vr
RT8876A 22 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. RT8876A 1 2 v 1 2 v 5v isenan isenap vcc5 pwma en fba compa imonfba imonfb 34 33 16 29 28 24 36 31 30 tonseta tonset 43 42 ofsa 1 qrseta iccmaxa 23 32 vcc5 iccmax tempmax 21 22 gnd 57 (exposed pad) rset 9 dvid 13 v ccaxg_sense v cc_sense comp 10 fb 11 ocseta 37 vcc5 ocset 38 vcc5 26 chip enable qrset r ntc rgnda 27 ofs 14 v in v in dvida 2 vr_rdy 41 35 vdio vclk alert 17 18 19 vr_rdy vdio vclk alert vccio vrhot vrhot rt9612 vcc pwm boot ugate phase lgate pgnd tsen 40 r n t c vcc5 vcc12 48 12v isen1n isen1p lgate1 5 6 49 v in phase1 50 ugate1 51 boot1 52 isen3n isen3p lgate3 8 7 47 v i n phase3 46 ugate3 45 boot3 44 isen2n isen2p lgate2 4 3 53 v i n phase2 54 ugate2 55 boot2 56 v ssaxg_sense load v out_axg v s s _ s e n s e load v o u t _ c o r e rgnd 12 tsena 39 r n t c vcc5 ibias 20 imon 15 imona 25 r ntc 100 100 figure 2. thernal compersation at current loop for axg vr
RT8876A 23 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. RT8876A 5v isenan isenap vcc5 pwma en fba compa imonfba imonfb 34 33 16 29 28 24 36 31 30 tonseta tonset 43 42 ofsa 1 qrseta iccmaxa 23 32 vcc5 iccmax tempmax 21 22 gnd 57 (exposed pad) rset 9 dvid 13 v cc_sense comp 10 fb 11 ocseta 37 ocset 38 vcc5 26 chip enable qrset r ntc rgnda 27 ofs 14 v in dvida 2 vr_rdy 41 35 vdio vclk alert 17 18 19 vr_rdy vdio vclk alert vccio vrhot vrhot tsen 40 r n t c vcc5 vcc12 48 12v isen1n isen1p lgate1 5 6 49 v in phase1 50 ugate1 51 boot1 52 isen3n isen3p lgate3 8 7 47 v i n phase3 46 ugate3 45 boot3 44 isen2n isen2p lgate2 4 3 53 v i n phase2 54 ugate2 55 boot2 56 v s s _ s e n s e load v out_core rgnd 12 tsena 39 ibias 20 imon 15 imona 25 floating 5v 100 figure 3. application circuit for axg vr being disabled
RT8876A 24 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics core vr power on time (100 s/div) v core (1v/div) v core = 1.1v, i load = 5a vr_rdy (2v/div) vdio (1v/div) alert (2v/div) core vr power off from en time (1ms/div) v core (1v/div) vr_rdy (2v/div) en (2v/div) pwm1 (5v/div) v core = 1.1v, i load = 5a core vr dynamic vid down time (40 s/div) vclk (1v/div) alert (2v/div) vdio (2v/div) v core = 1.2v down to 0.7v, i load = 20a fast slew rate v core (500mv/div) core vr dynamic vid down time (100 s/div) vclk (1v/div) alert (2v/div) vdio (2v/div) slow slew rate v core (500mv/div) v core = 1.2v down to 0.7v, i load = 20a core vr dynamic vid up time (40 s/div) v core (500mv/div) vclk (1v/div) alert (2v/div) vdio (2v/div) v core = 0.7v up to 1.2v, i load = 20a fast slew rate core vr dynamic vid up time (100 s/div) vclk (1v/div) alert (2v/div) vdio (2v/div) v core = 0.7v up to 1.2v, i load = 20a slow slew rate v core (500mv/div)
RT8876A 25 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v imon vs. load current 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 0 102030405060708090100 load current (a) v imon (v) core vr load transient response time (100 s/div) v core (50mv/div) v core = 1.1v, f load = 300hz, i load = 5a to 70a 70a 5a i load core vr load transient response time (100 s/div) v core = 1.1v, f load = 300hz, i load = 70a to 5a 70a 5a i load v core (50mv/div) core vr ocp time (100 s/div) v core = 1.1v v core (2v/div) vr_rdy (2v/div) pwm1 (5v/div) i load (100a/div) core vr uvp time (1ms/div) v core = 1.1v, i load = 1a v core (1v/div) vr_rdy (1v/div) pwm1 (5v/div) core vr ovp & nvp time (40 s/div) v core (1v/div) vr_rdy (1v/div) pwm1 (5v/div) v core = 1.1v
RT8876A 26 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. axg vr dynamic vid up time (40 s/div) v axg (500mv/div) vclk (2v/div) vdio (2v/div) alert (2v/div) v axg = 0.7v up to 1.2v, i load = 20a fast slew rate axg vr dynamic vid up time (100 s/div) v axg = 0.7v up to 1.2v, i load = 20a v axg (500mv/div) vclk (2v/div) vdio (2v/div) alert (2v/div) slow slew rate axg vr dynamic vid down time (40 s/div) v axg = 1.2v down to 0.7v, i load = 20a v axg (500mv/div) vclk (2v/div) vdio (2v/div) alert (2v/div) fast slew rate axg vr dynamic vid down time (100 s/div) v axg = 1.2v down to 0.7v, i load = 20a v axg (500mv/div) vclk (2v/div) vdio (2v/div) alert (2v/div) slow slew rate axg vr power off from en v axg (1v/div) en (1v/div) pwma (10v/div) v axg = 1.1v, i load = 5a time (1ms/div) axg vr power on v axg = 1.1v, i load = 5a v axg (1v/div) vdio (1v/div) alert (1v/div) time (100 s/div)
RT8876A 27 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v imona vs. load current 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 0 3 6 9 12 15 18 21 24 27 30 load current (a) v imona (v) axg vr load transient response time (100 s/div) v axg (50mv/div) v axg = 1.1v, f load = 300hz, i load = 2a to 22a 22a 2a i load axg vr load transient response time (100 s/div) v axg (50mv/div) 22a 2a i load v axg = 1.1v, f load = 300hz, i load = 22a to 2a axg vr ocp time (100 s/div) v axg = 1.1v v axg (2v/div) pwma (10v/div) i load (50a/div) axg vr ovp & nvp time (100 s/div) v axg (1v/div) pwma (5v/div) v axg = 1.1v axg vr uvp time (1ms/div) v axg = 1.1v, i load = 1a v axg (1v/div) pwma (5v/div)
RT8876A 28 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. thermal monitoring time (400 s/div) tsen from 1.7v sweep to 1.9v, i load = 0a tsen (100mv/div) vrhot (1v/div)
RT8876A 29 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 4. power ready (por) detection application information the RT8876A is a cpu power controller which includes two channels : a 3/2/1 phase synchronous buck controller with three integrated drivers for core vr, and a single phase buck controller for axg vr. the RT8876A is compliant with intel vr12/imvp7 voltage regulator specification to fulfill intel's cpu power supply requirements of both core and axg voltage regulators. a serial vid (svid) interface is built-in in the RT8876A to communicate with intel vr12/imvp7 compliant cpu. the RT8876A adopts g-navp tm (green native adaptive voltage positioning), which is richtek's proprietary topology derived from finite dc gain ea amplifier with current mode control, making it an easy setting pwm controller, meeting all intel cpu requirements of avp. the load line can be easily programmed by setting the dc gain of the error amplifier. the RT8876A has fast transient response because of the g-navp tm commanding variable switching frequency. based on the g-navp tm topology, the RT8876A also features a quick response mechanism so that fully phases can respond for optimized avp performance during load transient. the g-navp tm topology also represents a high efficiency system with green power concept. with the g-navp tm topology, the RT8876A is also a green power controller with high efficiency under heavy load, light load, and very light load conditions. the RT8876A supports mode transition function with various operating states, including multi-phase, single phase and dem (diode emulation modes). these different operating states allow the overall power control system to have the lowest power loss. by utilizing the g-navp tm topology, the operating frequency of the RT8876A varies with vid, load, and input voltage to further enhance the efficiency even in ccm. the built-in high accuracy dac converts the svid code ranging from 0.25v to 1.52v with 5mv per step. the RT8876A supports vid on-the-fly function with three different slew rates : fast, slow and decay. the RT8876A also builds in a high accuracy adc for some platform setting functions, such as no-load offset or over current level. the controller supports both dcr and sense resistor current sensing. the RT8876A provides power vr ready signals for both core vr and axg vr. it also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. the RT8876A is available in a wqfn-56l 7x7 small footprint package. general loop functions : power ready (por) detection during start-up, the RT8876A will detect the voltage at the voltage input pins : vcc5, vcc12 and en. when vcc5 > 4.24v and vcc12 > 4v, the RT8876A will recognize the power state of system to be ready (por = high) and wait for enable command at the en pin. after por = high and v en > 0.7v, the RT8876A will enter start- up sequence for both core rail and axg rail. if the voltage at any voltage pin drops below low threshold (por = low), the RT8876A will enter power down sequence and all the functions will be disabled. normally, connecting system v tt (1.05v) to the en pin and power stage v in (12v) to the vcc12 pin is recommended. 2ms (max) after the chip has been enabled, the svid circuitry will be ready. all the protection latches (ovp, ocp, uvp) will be cleared only after por = low. the condition of v en = low will not clear these latches. precise reference current generation the RT8876A includes complicated analog circuits inside the controller. these analog circuits need very precise reference voltage/current to drive these analog devices. the RT8876A will auto generate a 2.14v voltage source at the ibias pin, and a 53.6k resistor is required to be connected between ibias and analog ground. through this connection, the RT8876A will generate a 40 a current from the ibias pin to analog ground, and this 40 a current + - + - + - por chip en 4.24v 1.06v 0.7v vcc5 vcc12 en + - 1.06v + - 4v
RT8876A 30 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 5. ibias setting figure 6. adc pins setting + - ibias 53.6k current mirror + - 2.14v will be mirrored inside the RT8876A for internal use. note that other types of connection or other values of resistance applied at the ibias pin may cause failure of the RT8876A's functions, such as slew rate control, ofs accuracy, etc. in other words, the ibias pin can only be connected with a 53.6k resistor to gnd. the resistance accuracy of this resistor is recommended to be 1% or higher. iccmax, iccmaxa and tempmax the RT8876A provides iccmax, iccmaxa and tempmax pins for platform users to set the maximum level of output current or vr temperature : iccmax for core vr max current, iccmaxa for axg vr max current, and tempmax for core vr max temperature. to set iccmax, iccmaxa and tempmax platform designers should use resistive voltage divider on these three pins. the current of the divider should be several milliamps to avoid noise effect. the 3 items share the same algorithms : the adc divides 5v into 255 levels. therefore, the lsb = 5 / 255 = 19.6mv, which means 19.6mv applied to iccmax pin equals to 1a setting. for example, if the maximum level of temperature is desired to be 120 c, the voltage applied to tempmax should be 120 x 19.6mv = 2.352v. the adc circuit inside these three pins will decode the voltage applied and store the maximum current/temperature setting into icc_max and temp_max registers. the adc monitors and decodes the voltage at these three pins only once after power up. after adc decoding (only once), a 128 a current will be generated at the iccmaxa pin for internal use. make sure the voltage at the iccmaxa pin is greater than 1.55v to guarantee proper functionality the RT8876A will not take any action even when the vr output current or temperature exceeds its maximum setting at these adc pins. the maximum level settings at these adc pins are different from over current protection or over temperature protection. in other words, these maximum level setting pins are only for platform users to define their system operating conditions and these messages will only be utilized by the cpu. v initial setting the vr's v initial can be selected as 0v or 1.1v by qrset pin. the connection of the qrset pin is usually a voltage divider circuit which is described later in the quick response section in core rail part. before por, the RT8876A will source an 80 a current from the qrset pin to the external voltage divider to determine the voltage level while the RT8876A is still not powered on. before por, if the voltage at the qrset pin is higher than v cc5 ? 0.5v, the v initial will be 1.1v. if the voltage is lower than v cc5 ? 1.8v, the v initial will be 0v. for example, a 5v voltage divided by two 1k resistors connected to the qrset pin generates 2.54v (5v / 2 + 80 a x 1k / 2) before por and 2.5v (5v/2) after por. so the v initial will be 0v under this condition. please note that the both core rail and axg rail are simultaneously set as v initial = 1.1v or 0v. vr rail addressing the vr's address can be flipped by setting qrseta pin. the connection of the qrseta pin is usually a voltage divider circuit which is described later in the quick response section in axg rail part. before por, the RT8876A will source an 80 a current from the qrseta pin to the external voltage divider to determine the voltage level while the RT8876A is still not powered on. before a/d converter iccmax iccmaxa tempmax v cc5 i
RT8876A 31 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7 (a). power sequence for v initial = 0v por, if the voltage at the qrseta pin is lower than v cc5 ? 1.8v, the address will be flipped, that is, vr0 (core) address is flipped from 0000 to 0001 and vr1 (axg) address is flipped from 0001 to 0000. for example, a 5v voltage divided by two 1k resistors connected to the qrseta pin generates 2.54v (5v / 2 + 80 a x 1k / 2) before por and 2.5v (5v/2) after por. so the address will be flipped under this condition. start-up sequence the RT8876A utilizes an internal soft-start sequence which strictly follows intel vr12/imvp7 start-up sequence specifications. after por = high and en = high, the controller considers all the power inputs ready and enters start-up sequence. if v initial = 0v, v out is programmed to stay at 0v for 2ms waiting for svid command. if v initial = 1.1v, vout will ramp up to v initial voltage (which is not zero) immediately after both por = high and en = high. after v out reaches target v initial , v out will stay at v initial waiting for svid command. after the RT8876A receives valid vid code (typically setvid_slow command), v out will ramp up to the target voltage with specified slew rate (see section ? data and configuration register ? ). after v out reaches target voltage (vid voltage for v initial = 0v or v initial for v initial = 1.1v), the RT8876A will send out vr_rdy signal to indicate that the power state of the RT8876A is ready. the vr ready circuit is an open-drain structure, so a pull-up resistor connected to a voltage source is recommended. power down sequence similar to the start-up sequence, the RT8876A also utilizes a soft shutdown mechanism during turn-off. after en = low, the internal reference voltage (positive terminal of compensation ea) starts ramping down with 3.125mv/ s slew rate, and v out will follow the reference voltage to 0v. after v out drops below 0.2v, the RT8876A shuts down and all functions (drivers) are disabled. the vr_rdy will be pulled down immediately after por = low or en = low. en vcc5 4.2v 3.7v svid valid xx xx por 4v 3.5v vcc12 v out,core svid defined hi-z ugate hi-z 0.2v max phases max phases 2ms vr_rdy 100s v out,axg 0.2v svid defined hi-z pwma hi-z 1 phase ccm 1 phase ccm
RT8876A 32 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7 (b). power sequence for v initial = 1.1v core vr active phase determination : before por the number of active phases is determined by the internal circuitry that monitors the isenxn voltages during start- up. normally, the core vr operates as a 3-phase pwm controller. pulling isen3n to vcc5 programs a 2-phase operation, pulling isen3n and isen2n to vcc5 programs a 1-phase operation. before por, core vr detects whether the voltages of isen2n and isen3n are higher than ? vcc5 ? 1v ? respectively to decide how many phases should be active. phase selection is only active during por. when por = high, the number of active phases is determined and latched. the unused isenxp pins are recommended to be connected to vcc5. loop control introduction the core vr adopts richtek's proprietary g-navp tm topology. g-navp tm is based on the finite gain peak current mode with ccrcot (constant current ripple constant on-time) topology. the control loop consists of pwm modulators with power stages, current sense amplifiers and an error amplifier as shown in figure 8. similar to the peak current mode control with finite compensator gain, the hs_fet on-time is determined by ccrcot on-time generator. when load current increases, v cs increases, the steady state comp voltage also increases and induces v out,core to decrease, thus achieving avp to meet intel's load line specification. a near-dc offset canceling is added to the output of ea to eliminate the inherent output offset of finite gain peak current mode controller. v out,core svid defined hi-z ugate hi-z 0.2v max phases max phases 2ms vr_rdy 100s v out,axg 0.2v svid defined hi-z pwma hi-z 1 phase ccm 1 phase ccm v initial = 1.1v v initial = 1.1v en vcc5 4.2v 3.7v svid valid xx xx por 4v 3.5v vcc12
RT8876A 33 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 10. loop setting with temperature compensation usually, r1a is set to equal r ntc (25 c). r1b is selected to linearize the ntc's temperature characteristic. for a given ntc, design is to get r1b and r2 and then c1 and c2. according to equation (2), to compensate the temperature variations of the sense resistor, the error amplifier gain (a v ) should have the same temperature coefficient with r sense . hence from equation (2), a v can be obtained at any temperature (t c) as shown below : the standard formula for the resistance of ntc thermistor as a function of temperature is given by : where r 25 c is the thermistor's nominal resistance at room temperature, is the thermistor's material constant in kelvins, and t is the thermistor's actual temperature in celsius. the dcr value at different temperature can be calculated by the following equation : dcr t c = dcr 25 c x [1 + 0.00393 x (t ? 25)] (6) where 0.00393 is the temperature coefficient of copper. for a given ntc thermistor, solving equation (4) at room temperature (25 c) yields : v, hot sense, hot v, cold sense, cold ar ar = (3) v, t c ntc, t c r2 a r1a // r r1b = + (4) ( ) ( ) { } ?? ? ?? ?? = 11 t+273 298 ntc, t c 25 c rr e (5) v cc_sense - + v ss_sense fb rgnd comp c2 c1 r2 r1b ea r1a r ntc - + vdac figure 8. core vr : simplified schematic for droop and remote sense in ccm droop setting (with temperature compensation) it's very easy to achieve active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics. the target is to have v out = v dac ? i load x r droop (1) then solving the switching condition v comp2 = v cs in figure 8 yields the desired error amplifier gain a v as where a i is the internal current sense amplifier gain 10v/ v. r sense is the current sense resistor. figure 9 shows the error amplifier gain (a v ) influence on v out accuracy according to equation (2). in general, the dcr of the inductor is adopted as r sense to achieve lossless current sensing method. r droop is the equivalent load line resistance as well as the desired static output impedance. (2) figure 9. error amplifier gain (a v ) influence on load line i sense v droop ar r2 a r1 r == a v1 a v2 a v2 > a v1 v out load current 0 since the dcr of the inductor is temperature dependent, it affects the output accuracy at hot conditions. temperature compensation is recommended for the lossless inductor dcr current sense method. figure 10 shows a simple but effective way of compensating the temperature variations of the sense resistor using an ntc thermistor placed in the feedback path. v out, core v cc_sense + - isenxp isenxn a i + - cmp v cs comp2 - + v in, core fb rgnd comp hs_fet ls_fet l r x c x r c c c2 c1 r2 r1 ea - + v ss_sense v dac, core offset canceling ccrcot pwm logic driver lgatex ugatex
RT8876A 34 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. on time control is adopted in RT8876A, a constant on time can be set by connecting a resistor from vin to tonset pin first, and then the switching frequency of the regulator can be decided to apply in different applications. figure 11 shows the on-time setting circuit. connect a resistor (r ton ) between v in,core and tonset to set the on-time of ugate : (12) ? <= ? 12 ton on dac in dac 24.4 10 r t (v 1.2v) vv where t on is the ugate turn on period, v in is input voltage of the core vr, and v dac is the dac voltage. when vdac is larger than 1.2v, the equivalent switching frequency may be over 500khz, and this too fast switching frequency is unacceptable. therefore, the core vr implements a pseudo constant frequency technology to avoid this disadvantage of ccrcot topology. when v dac is larger than 1.2v, the on-time equation will be modified to : (13) ? = ? 12 ton dac on dac in dac 20.33 10 r v t (v 1.2v) vv during ps2/ps3 operation, the core vr shrinks its on- time for the purpose of reducing output voltage ripple caused by dcm operation. the shrink percentage is 15% compared with original on-time setting by equation (12) or (13). that is, after setting the ps0 operation on-time, the ps2/ps3 operation on-time is 0.85 times the original on-time. on-time translates only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in external hs-fet. also, the dead-time effect increases the effective on-time, which in turn reduces the switching frequency. it occurs only in ccm and during dynamic output voltage transitions, when the inductor current reverses at light or negative load currents. with reversed inductor current, the phase goes high earlier than normal, extending the on-time by a period equal to the hs-fet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : (14) ? ? ?? = ? ?? + +? ?? ?? + ? ?? s(max) on hs delay dac(max) load(max) on _ ls fet droop in(max) load(max) on _ ls fet on _ hs fet 1 f(khz) tt vi r dcrr vi r r loop compensation optimized compensation of the core vr allows for best possible load step response of the regulator's output. a type-i compensator with one pole and one zero is adequate for proper compensation. figure 10 shows the compensation circuit. previous design procedure shows how to select resistive feedback components for the error amplifier gain. next, c1 and c2 must be calculated for compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : where c is the capacitance of output capacitor, and r c is the esr of output capacitor. c2 can be calculated as follows : = ? ?? ? ?? ?? sense, hot ntc, hot ntc, cold sense, cold sense, hot sense, cold r1b r (r1a / /r ) (r1a // r ) r r 1 r (8) = p c 1 f 2cr (9) = c cr c2 r2 (10) r2 = a v, 2 5 c x (r1b + r1a // r ntc, 25 c ) (7) where a v, 2 5 c is the error amplifier gain at room temperature and can be obtained from equation (2). r 1b can be obtained by substituting (7) for (3), the zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that, (11) () ntc, 25 c sw 1 c1 r1b r1a // r f = + ton setting high frequency operation optimizes the application for the smaller component size, trading off efficiency due to higher switching related losses. this may be acceptable in ultra portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space. constant
RT8876A 35 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 12. core vr : lossless inductor sensing isenxp isenxn l dcr r x c x + v x - v out, core figure 11. core vr : on-time setting with r c filter where f s(max) is the maximum switching frequency, t hs- delay is the turn-on delay of hs-fet, v dac(max) is the maximum vdac of application, v in(max) is the maximum application input voltage, i load(max) is the maximum load of application, r on_ls-fet is the low side fet r ds(on) , r on_hs-fet is the high side fet r ds(on) ,dcr is the inductor dcr, and r droop is the load line setting. differential remote sense setting the core vr includes differential, remote-sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. the cpu contains on-die sense pins, v cc_sense and v ss_sense . connect rgnd to v ss_sense . connect fb to v cc_sense with a resistor to build the negative input path of the error amplifier. the v dac and the precision voltage reference are referred to rgnd for accurate remote sensing. current sense setting the current sense topology of the core vr is continuous inductor current sensing. therefore, the controller can be less noise sensitive. low offset amplifiers are used for loop control and over current detection. the internal current sense amplifier gain (ai) is fixed to be 10. the isenxp and isenxn denote the positive and negative input of the current sense amplifier of any phase. users can either use a current sense resistor or the inductor's dcr for current sensing. using the inductor's dcr allows higher efficiency because of lossless characteristic as shown in figure 12. refer to below equation for optimum transient performance : x x l rc dcr = (15) (16) == ? x 0.36 h r3.6k 1m 1 0 0 n f considering the inductance tolerance, the resistor r x has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, r x is chosen too small. vice versa, with a resistance too large the output voltage transient has only a small initial dip and the recovery is too fast causing a ring back. using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current sense resistor, an rc filter is recommended. the rc filter calculation method is similar to the above mentioned inductor dcr sensing method. current balance the core vr implements internal current balance mechanism in the current loop. the core vr senses and compares per-phase current signal with average current. if the sensed current of any particular phase is larger than average current, the on-time of this phase will be adjusted to be shorter, vice versa. no load offset (svid & platform) the core vr features no load offset function which provides the possibility of wide range positive offset of output voltage. the no-load offset function can be implemented through the svid interface or ofs pin. users can disable pin offset function by simply connecting ofs pin to gnd. the RT8876A will latch the ofs status after por. if pin offset function is enabled, that the ofs pin voltage is more than 0.6v before por. ccrcot on-time computer tonset r ton r1 c1 v in, core vdac on-time
RT8876A 36 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dynamic vid enhancement during a dynamic vid event, the charging (dynamic vid up) or discharging (dynamic vid down) current causes unwanted load-line effect which degrades the settling time performance. the dvid pin can be used to compensate the load-line effect, so that the output voltage can be settled to the target value more quickly. during a dynamic vid up event occurred, the RT8876A sources out a current (i dvid ) to dvid pin. the voltage on dvid pin is added to dac during dvid rising to enhance the dynamic vid performance. connecting a capacitor in parallel with a resistor to dvid pin is recommended. i dvid is 8 a during a setvid_fast event. if it is a setvid_slow event, i dvid automatically shrinks to 2 a (if slow slew rate is 0.25 x fast slew rate). this function is null during a dynamic vid down event. the pin offset voltage is set by supplying a voltage into ofs pin. the linear range of offset pin voltage is from 0.9v to 1.83v. the pin offset voltage can be calculated as below : ? ? pin ofs ofs v = v1.2v (17) (18) for example, supplying 1.3v at ofs pin will achieve 100mv offset at the output. connecting a filter capacitor between the ofs pin and gnd is necessary. operation mode transition RT8876A supports operation mode transition function at the core vr for the setps command of intel's vr12/ imvp7 cpu. the default operation mode of the core vr is ps0, which is full phase ccm operation. other operation modes include ps1 (single phase ccm operation) and ps2 (single phase dem operation). after receiving setps command, the core vr will immediately change to the new operation state. when the core vr receives setps command of ps1 operation mode, the core vr operates as a single phase ccm controller, and only channel 1 is active. the core vr will disable phase 2 and phase 3 by disabling internal pwm logic drivers (pwm = high impedance state). therefore, 2 internal drivers which support tri-state shutdown are also required for compatibility with ps1 operation mode. similarly, when the core vr receives setps command of ps2 operation mode, the core vr operates as a single phase dcm controller, and only channel 1 is active with diode emulation operation. the core vr will disable phase 2 and phase 3 by disabling internal pwm logic drivers (pwm = high impedance state). therefore, all internal drivers which support tri-state shutdown are required for compatibility with ps2 operation state. if the core vr receives dynamic vid change command (setvid), the core vr will automatically enter ps0 operation mode and all phases will be activated. after v out,core reaches target voltage, the core vr will stay at ps0 state and ignore former setps command. only re-sending setps command after setvid command will the core vr be forced into ps1 or ps2 operation states again. figure 13. dvid compensation circuit ramp amplitude adjust when the core vr enters ps2 operation mode, the internal ramp of core vr will be modified for the reason of stability. in case of smooth transition into ps2, the ccm ramp amplitude should be designed properly. the RT8876A provides rset pin for platform users to set the ramp amplitude of the core vr in ccm. the criteria is to set the ramp amplitude proportional to the on-time (when v dac <1.2v). the equation will be : 57.6 x 10 ? 12 = t on x (v in ? v dac ) x 1 / rset (19) where 57.6 x 10 ? 12 is an internal coefficient of analog circuit. according to equation (12), the rset equation can be simplified to : r rset = 0.4236 x r ton (20) 1/20 ea + dvid event i dvid + - slew rate control dac fb dvid if then the output voltage is : ? ? =? out dac load droop pin ofs svid ofs vvi r + v + v
RT8876A 37 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. where the v imon(max) is the maximum voltage at full load, and i max is the full load current of vr. table 4. temperature_zone register vrhot svid thermal aler t comparator trip points temperatures scaled to maximum = 100% voltage represents assert bit minimum level b7 b6 b5 b4 b3 b2 b1 b0 100% 97% 94% 91% 88% 85% 82% 75% 1.845v 1.79v 1.735v 1.68v 1.625v 1.57v 1.515v 1.46v = load droop imon imon imonfb i x r x r v r (21) figure 14. core vr : thermal monitoring circuit current monitoring and current reporting the core vr provides current monitoring function via sensing the voltage difference of imonfb pin and output the vrhot pin is an open-drain structure that sends out active low vrhot signal. when b6 of temperature_zone register asserts to 1 (when tsen voltage rises above 1.79v), the alert signal will be asserted to low, which is so-called svid thermal alert. in the mean time, the core vr will assert bit 1 data to 1 in status_1 register. the alert assertion will be de-asserted when b5 of temperature_zone register is de-asserted from 1 to 0 (which means tsen voltage falls under 1.735v), and bit 1 of status_1 register will also be cleared to 0. the bit 1 assertion of status_1 is not latched and cannot be cleared by getreg command. when b7 of temperature_zone register asserts to 1 (when tsen voltage rises above 1.845v), the vrhot signal will be asserted to low. the vrhot assertion will be de-asserted when b6 of temperature_zone register is de-asserted from 1 to 0 (which means tsen voltage falls under 1.79v). it is typically recommended to connect a pull-up resistor from the vrhot pin to a voltage source. where i load is the output load current, r droop is the equivalent load line resistance, and r imon and r imonfb are the current monitor current setting resistors. in vr12/ imvp7 specification, the voltage signal of current monitoring will be restricted by a maximum value. platform designers have to select r imon to meet the maximum voltage of imon at full load. to find r imon and r imonfb based on : tsen vcc5 r3 r1 r ntc r2 thermal monitoring and temperature reporting the core vr provides thermal monitoring function via sensing tsen pin voltage. through the voltage divider resistors, r1 and r ntc , the voltage of tsen will be proportional to vr temperature. when vr temperature rises, tsen voltage also rises. the adc circuit of the core vr monitors the voltage variation at the tsen pin from 1.46v to 1.845v with 55mv resolution. this voltage is then decoded into digital format and stored into temperature_zone register. to meet intel's vr12/imvp7 specification, platform users have to set the tsen voltage to meet the temperature variation of vr from 75% to 100% vr max temperature. for example, if the vr max temperature is 100 c, platform users have to set the tsen voltage to be 1.515v when vr temperature reaches 82 c and 1.845v when vr temperature reaches 100 c. detailed voltage setting versus temperature variation is shown in table 4. the thermometer code is implemented in temperature_zone register. voltage. in g-navp tm technology, the output voltage is dependent on output current, and the current monitoring function is achieved by this characteristic of output voltage. figure 15 shows the current monitoring setting principle. the equivalent output current will be sensed from imonfb pin and mirrored to imon pin. the resistor connected to imon pin determines voltage gain of the imon output. the current monitor indicator equation is shown as : = imon(max) imon imonfb max droop v r ri x r (22)
RT8876A 38 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 15. core vr : current monitoring circuit current mirror imonfb + - r imonfb v cc_sense i mirror r imon imon fb figure 16. core vr : quick response triggering circuit ? = = ? qrset on, qr on 12 ton qrset in dac v tt 1.2 20.33 10 r v vv (23) after generating a quick response pulse, the pulse is then applied to the on-time generation circuit, and all the active phases on-times will be overridden by the quick response pulse. over current protection the core vr compares a programmable current limit set point to the voltage from the current sense amplifier output of each phase for over current protection (ocp). therefore, the ocp mechanism of the RT8876A implements per-phase current protections. the voltage applied to the ocset pin defines the desired current limit threshold, i limit_core : v ocset = 48 x i limit_core x r sense (24) quick response the core vr utilizes a quick response feature to support heavy load current demand during instantaneous load transient. the core vr monitors the current of the imonfb pin, and this current is mirrored to internal quick response circuit. at steady state, this mirrored current will not trigger a quick response. when the v out, core voltage drops abruptly due to load apply transient, the mirrored current flowing into quick response circuit will also increase instantaneously. when the mirrored current instantaneously rises above 5 a, quick response will be triggered. when quick response is triggered, the quick response circuit will generate a quick response pulse. the internal quick response pulse generation circuit is similar to the on-time generation circuit. the only difference is the qrset pin. the voltage at the qrset pin also influences the pulse width of quick response. a voltage divider circuit is recommended to be applied to the qrset pin. therefore, with a little modification of equation (12), the pulse width of quick response pulse can be calculated as : the adc circuit of the core vr monitors the voltage variation at the imon pin from 0v to 3.3v, and this voltage is decoded into digital format and stored into output_current register. the adc divides 3.3v into 255 levels, so lsb = 3.3v/255 = 12.941mv. platform designers should design v imon to be 3.3v at i ccmax . for example, when load current = 50% x i ccmax , v imon = 1.65v and output_current register = 7fh. the imon pin is an output of the internal operational amplifier and sends out imon signal. when the data of output_current register reaches 255d (when imon voltage rises above 3.3v), the alert signal will be asserted to low, which is so-called svid iccmax alert. in the mean time, the core vr will assert the bit 2 data to 1 in status_1 register. the alert assertion will be de-asserted when the data of output_current register decreases to 242d (when imon voltage falls under 3.144v). the bit 2 assertion of status_1 register is latched and can only be cleared when two criteria are met : the data of output_current register decreases to 242d (when imon voltage falls under 3.144v) and the getreg command is sent to the status_1 register of the core vr. current mirror imonfb + - vdac r imonfb v cc_sense i mirror qr trigger (25) ?? = ? ?? ?? cc5 oc1 oc2 ocset v rr 1 v connect a resistive voltage divider from vcc5 to gnd, and the joint of the resistive voltage divider is connected to the ocset pin as shown in figure 17. for a given r oc2 ,
RT8876A 39 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. re-write (27) from (26) to get v ocset at room temperature solvin g (28) and (29) yield s r oc1b and r oc2 ++ = ++ oc1a ntc, cold oc1b oc2 sense, hot oc1a ntc, hot oc1b oc2 sense, cold r // r r r r r// r r r r (28) (29) = ++ ocset, 25 c oc2 cc5 oc1a ntc, 25 c oc1b oc2 v r v r // r r r (30) = ? + ? ? oc2 equ, hot equ, cold equ, 25 c cc5 ocset, 25 c r rr (1)r v (1 ) v (31) = ? + ? ? oc1b oc2 equ, hot equ, cold r (1)r r r (1 ) where = + ? = + ? sense, hot 25 c hot sense, cold 25 c cold r dcr [1 0.00393 x (t 25)] r dcr [1 0.00393 x (t 25)] (32) figure 17. ocp setting without temperature compensation the current limit is triggered when per-phase inductor current exceeds the current limit threshold, i limit_core , as defined by v ocset . the driver will then be forced to turn off ugate until the condition is cleared. if the over current condition of any phase remains valid for 15 cycles, the core vr will trigger ocp latch. latched ocp forces pwm into high impedance, which disables internal pwm logic drivers. if the over current condition is not valid for 15 continuous cycles, the ocp latch counter will be reset. when ocp is triggered by the core vr, the axg vr will also enter soft shut down sequence. if inductor dcr is used as the current sense component, temperature compensation is recommended for proper protection under all conditions. figure 18 shows a typical ocp setting with temperature compensation. usually, r oc1a is selected to be equal to the thermistor's nominal resistance at room temperature. ideally, assume v ocset has the same temperature coefficient as r sense (inductor dcr) : figure 18. ocp setting without temperature compensation ocset v cc5 r oc1b r oc2 r oc1a ntc r equ, t c = r oc1a // r ntc, t c (33) over voltage protection (ovp) the over voltage protection circuit of the core vr monitors the output voltage via the isen1n pin after por. the supported maximum operating vid of the vr (v (max) ) is stored in the vout_max register. once v isen1n exceeds ? v (max) + 150mv ? , ovp is triggered and latched. the core vr will try to turn on low side mosfets and turn off high side mosfets of all active phases of the core vr to protect the cpu. when ovp is triggered by the core vr, the axg vr will also enter soft shut down sequence. a 1 s delay is used in ovp detection circuit to prevent false trigger. note that if ofs pin is higher than 0.9v before power up, ovp will trigger at ? v (max) + 850mv ? . v cc5 ocset r oc1 r oc2 ocset, hot sense, hot ocset, cold sense, cold vr vr = (26) according to the basic circuit calculation, we can get v ocset at any temperature : = ++ ocset, t c oc2 cc5 oc1a ntc, t c oc1b oc2 v r v r// r r r (27)
RT8876A 40 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. negative voltage protection (nvp) during ovp latch state, the core vr also monitors the isen1n pin for negative voltage protection. since the ovp latch will continuously turn on all low side mosfets of the core vr, the core vr may suffer negative output voltage. as a consequence, when the isen1n voltage drops below ? 0.05v after triggering ovp, the core vr will trigger nvp to turn off all low side mosfets of the core vr while the high side mosfets remains off. after triggering nvp, if the output voltage rises above 0v, the ovp latch will restart to turn on all low side mosfets. therefore, the output voltage may travel between 0v and ? 0.05v due to ovp latch and nvp triggering. the nvp function will be active only after ovp is triggered. a 1 s delay is used in nvp detection circuit to prevent false trigger. under voltage protection (uvp) the core vr implements under voltage protection of v out,core . if isen1n is less than the internal reference by 300mv, the core vr will trigger uvp latch. the uvp latch will turn off both high side and low side mosfets. when uvp is triggered by the core vr, the axg vr will also enter soft shut down sequence. a 3 s delay is used in uvp detection circuit to prevent false trigger. if platform ofs function is enabled (ofs pin not connected to gnd), the uvp function will be disabled. under voltage lock out (uvlo) during normal operation, if the voltage at the vcc5 or vcc12 pin drops below por threshold, the core vr will trigger uvlo. the uvlo protection forces all high side mosfets and low side mosfets off by shutting down internal pwm logic drivers. a 3 s delay is used in uvlo detection circuit to prevent false trigger. axg vr axg vr disable the axg vr can be disabled by connecting isenan to a voltage higher than ? v cc5 ? 1v ? . if not in use, isenap and tsena are recommended to be connected to vcc5, while pwma is left floating. when axg vr is disabled, all svid commands related to axg vr will be rejected. loop control the axg vr adopts richtek's proprietary g-navp tm topology. g-navp tm is based on the finite gain peak current mode with ccrcot (constant current ripple constant on-time) topology. the output voltage, v out, axg , will decrease with increasing output load current. the control loop consists of a pwm modulator with power stage, a current sense amplifier and an error amplifier as shown in figure 19. similar to the peak current mode control with finite compensator gain, the hs_fet on-time is determined by ccrcot on-time generator. when load current increases, v cs increases, steady state compa voltage also increases and induces v out, axg to decrease, thus achieving avp. a near-dc offset canceling is added to the output of ea to cancel the inherent output offset of finite- gain peak current mode controller. v out, axg v ccaxg_sense pwma + - isenap isenan a i + - cmp v cs compa2 - + v in, axg fba rgnda compa hs_fet ls_fet l r x c x r c c c2 c1 r2 r1 ea - + v ssaxg_sense v dac, core offset canceling driver ccrcot pwm logic figure 19. axg vr : simplified schematic for droop and remote sense in ccm droop setting (with temperature compensation) it's very easy to achieve active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics. the target is to have v out,axg = v dac,axg ? i load x r droop (34) , then solving the switching condition v comp2 = v cs in figure 19 yields the desired error amplifier gain as == isense v droop a x r r2 a r1 r (35) where a i is the internal current sense amplifier gain, r sense is the current sense resistance (an external sense resistor
RT8876A 41 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. where c is the capacitance of output capacitor, and r c is the esr of output capacitor. c2 can be calculated as below : the zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that, = p c 1 f 2cr (42) = c cr c2 r2 (43) (44) () = + ntc, 25 c sw 1 c1 r1b r1a // r f = ? ?? ? ?? ?? sense, hot ntc, hot ntc, cold sense, cold sense, hot sense, cold r1b r (r1a // r ) (r1a // r ) r r 1 r (41) the standard formula for the resistance of ntc thermistor as a function of temperature is given by : ( ) ( ) { } ?? ? ?? ?? = 11 t+273 298 ntc, t c 25 c rr e (38) from (33), av can be obtained at any temperature (t c) as : v, hot sense, hot v, cold sense, cold ar ar = (36) v, t c ntc, t c r2 a r1a // r r1b = + (37) figure 20. axg vr : loop setting with temperature compensation v ccaxg_sense - + v ssaxg_sense fba rgnda compa c2 c1 r2 r1b ea r1a r ntc - + v dac,axg or the dcr of the inductor), and r droop is the equivalent load line resistance as well as the desired static output impedance. since the dcr of the inductor is temperature dependent, the output accuracy may be affected at high temperature conditions. temperature compensation is recommended for the lossless inductor dcr current sense method. figure 20 shows a simple but effective way of compensating the temperature variations of the sense resistor by using an ntc thermistor placed in the feedback path. usually, r 1a is set to equal r ntc (25 c) and r 1b is selected to linearize the ntc's temperature characteristic. for a given ntc, the design procedure is to get r 1b and r2 first, and then c1 and c2 next. according to equation (35), to compensate the temperature variations of the sense resistor, the error amplifier gain (a v ) should have the same temperature coefficient as r sense . hence : where r 25 c is the thermistor's nominal resistance at room temperature, is the thermistor's material constant in kelvins, and t is the thermistor actual temperature in celsius. to calculate dcr value at different temperatures, use the equation below : dcr t c = dcr 25 c x [1+ 0.00393 x (t ? 25)] (39) where 0.00393 is the temperature coefficient of copper. for a given ntc thermistor, solving equation (37) at room temperature ( 25 c ) yields r2 = a v, 2 5 c x (r 1b + r 1a // r ntc, 25 c ) (40) where a v, 2 5 c is the error amplifier gain at room temperature and can be obtained from equation (35). r 1b can be obtained by substituting (40) to (36), loop compensation optimized compensation of the axg vr allows for best possible load step response of the regulator's output. a type-i compensator with one pole and one zero is adequate for a proper compensation. figure 20 shows the compensation circuit. previous design procedure shows how to select the resistive feedback components for the error amplifier gain. next, c1 and c2 must be calculated for compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : ton setting high frequency operation optimizes the application by allowing smaller component size, but with the trade-off of efficiency due to higher switching losses. this may be acceptable in ultra portable devices where the load currents
RT8876A 42 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space. figure 21 shows the on-time setting circuit. connect a resistor (r ton ) between v in,axg and tonseta pin to set the on-time of ugate : (45) ? <= ? 12 ton on dac in dac,axg 24.4 10 r t (v 1.2v) vv where t on is the ugate turn-on period, v in is the input voltage of the axg vr, and v dac, axg is the dac voltage. when v dac, axg is larger than 1.2v, the equivalent switching frequency may be too fast at over 500khz, which is unacceptable. therefore, the axg vr implements a pseudo constant frequency technology to avoid this disadvantage of ccrcot topology. when v dac, axg is larger than 1.2v, the on-time equation will be modified to : (46) ? = ? 12 ton dac, axg on dac in dac, axg 20.33 10 r v t (v 1.2v) vv on-time translates only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external hs- fet. also, the dead-time effect increases the effective on-time, which in turn reduces the switching frequency. it occurs only in ccm, and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the phase goes high earlier than normal, extending the on-time by a period equal to the hs-fet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : (47) ? ? ?? = ? ?? + +? ?? ?? + ? ?? s(max) on hs delay dac(max) load(max) on _ ls fet droop in(max) load(max) on _ ls fet on _ hs fet 1 f(khz) tt vi r dcrr vi r r where f s(max) is the maximum switching frequency, t hs- delay is the turn-on delay of hs-fet, v dac(max) is the maximum v dac, axg of application, v in(max) is the maximum application input voltage, i load(max) is the maximum load of application, r on_ls-fet is the low side fet r ds(on) , r on_hs-fet is the high side fet r ds(on) , dcr is the inductor dcr, and r droop is the load line setting. figure 21. axg vr : on-time setting with rc filter differential remote sense setting the axg vr includes differential, remote sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. the cpu contains on-die sense pins v ccaxg_sense and v ssaxg_sense . connect the rgnda to v ssaxg_sense . connect the fba to v ccaxg_sense with a resistor to build the negative input path of the error amplifier. the v dac,axg and the precision voltage reference are referred to rgnda for accurate remote sensing. current sense setting the current sense topology of the axg vr is continuous inductor current sensing. therefore, the controller can be less noise sensitive. low offset amplifiers are used for loop control and over current detection. the internal current sense amplifier gain (a i ) is fixed to be 20. the isenap and isenan denote the positive and negative input of the current sense amplifier. users can either use a current sense resistor or the inductor's dcr for current sensing. using inductor's dcr allows higher efficiency as shown in figure 22. refer to below equation for optimum transient performance : = x x l rc dcr (48) == ? x 0.36 h r3.6k 1m 1 0 0 n f (49) for example, choosing l = 0.36 h with 1m dcr and c x = 100nf yields : figure 22. axg vr : lossless inductor sensing ccrcot on-time computer tonseta r ton r1 c1 v in, axg v dac, axg on-time isenap isenan l dcr r x c x + v x - v out, axg
RT8876A 43 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 23. dvid compensation circuit 1/20 ea + dvid event i dvida + - slew rate control dac fba dvida ? ? =? out dac load droop pin ofs svid ofs vvi r + v + v ? ? pin ofsa ofsa v = v 1.2v (50) (51) considering the inductance tolerance, the resistor r x has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, r x is chosen too small. vice versa, if the resistance is too large the output voltage transient has only a small initial dip and the recovery becomes too fast, causing a ring back to occur. using current sense resistor in series with the inductor can have better accuracy, but at the expense of efficiency. considering the equivalent inductance (l esl ) of the current sense resistor, an rc filter is recommended. the rc filter calculation method is similar to the above mentioned inductor dcr sensing method. no load offset (svid & platform) the axg vr features no load offset function which provides the possibility of wide range positive offset of output voltage. the no load offset function can be implemented through the svid interface or ofsa pin. users can disable pin offset function by simply connecting ofsa pin to gnd. the RT8876A will latch the ofsa status after por. if pin offset function is enabled, the ofsa pin voltage is more than 0.6v before por. if then the output voltage is the pin offset voltage is set by supplying a voltage into ofsa pin. the linear range of offset pin voltage is from 0.9v to 1.83v. the pin offset voltage can be calculated as below : for example, supplying 1.3v at ofsa pin will achieve 100mv offset at the output. connecting a filter capacitor between the ofsa pin and gnd is necessary. operation mode transition the RT8876A supports operation mode transition function at axg vr for the setps command of intel vr12/imvp7 cpu. the default operation mode of the axg vr is ps0, which is ccm operation. other operation mode includes ps2 (single phase dem operation). after receiving setps command, the axg vr will immediately change to the new operation state. when the axg vr receives setps command of ps2 operation mode, the axg vr operates as a single phase dcm controller and diode emulation operation is activated. therefore, an external driver which supports tri-state shutdown is required for compatibility with ps2 operation state. if the axg vr receives dynamic vid change command (setvid), the axg vr will automatically enter ps0 operation mode. after v out, axg reach target voltage, axg vr will stay at ps0 state and ignore former setps command. only by resending setps command after setvid command will the axg vr be forced into ps2 operation state again. dynamic vid enhancement during a dynamic vid event, the charging (dynamic vid up) or discharging (dynamic vid down) current causes unwanted load-line effect which degrades the settling time performance. the dvida pin can be used to compensate the load-line effect, so that the output voltage can be settled to the target value more quickly. during a dynamic vid up event occurred, the RT8876A sources out a current (i dvida ) to dvida pin. the voltage on dvida pin is added to dac during dvid rising to enhance the dynamic vid performance. connecting a capacitor in parallel with a resistor to dvida pin is recommended. i dvida is 8 a during a setvid_fast event. if it is a setvid_slow event, i dvida automatically shrinks to 2 a (if slow slew rate is 0.25x fast slew rate). this function is null during a dynamic vid down event.
RT8876A 44 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 24. axg vr : thermal monitoring circuit table 5. temperature_zone register vrhot svid thermal alert b7 b6 100% 97% 1.845v 1.79v comparator trip points temperatures scaled to maximum = 100% voltage represents assert bit minimum level b5 b4 b3 b2 b1 b0 94% 91% 88% 85% 82% 75% 1.735v 1.68v 1.625v 1.57v 1.515v 1.46v thermal monitoring and temperature reporting the axg vr provides thermal monitoring function via sensing tsena pin voltage. through the voltage divider resistors, r1 and r ntc , the voltage of tsena will be proportional to vr temperature. when vr temperature rises, the tsena voltage also rises. the adc circuit of the axg vr monitors the voltage variation at the tsena pin from 1.46v to 1.845v with 55mv resolution. this voltage is then decoded into digital format and stored into temperature_zone register. to meet intel's vr12/imvp7 specification, platform users have to set the tsena voltage to meet the temperature variation of vr from 75% to 100% vr max temperature. for example, if the vr max temperature is 100 c, platform users have to set the tsena voltage to be 1.46v when vr temperature reaches 75 c and 1.845v when vr temperature reaches 100 c. detailed voltage setting versus temperature variation is shown in table 5. the thermometer code is implemented in temperature_zone register. current monitoring and current reporting the axg vr provides current monitoring function via sensing the imonfba pin. in g-navp tm technology, the output voltage is dependent on the output current, and the current monitoring function is achieved by this output voltage characteristic. figure 25 shows the current monitoring setting principle. the equivalent output current will be sensed from the imonfba pin and mirrored to the imona pin. the resistor connected to the imona pin determines the voltage gain of the imona output. the current monitor indicator equation is shown as : the vrhot pin is an open-drain structure that sends out active-low vrhot signal. when b6 of temperature_zone register asserts to 1 (when tsena voltage rises above 1.79v), the alert signal will be asserted to low, which is so-called svid thermal alert. in the mean time, the axg vr will assert the bit 1 data to 1 in status_1 register. the alert assertion will be de-asserted when b5 of temperature_zone register is de-asserted from 1 to 0 (which means tsena voltage falls under 1.735v), and the bit 1 of status_1 register will also be cleared to 0. the bit 1 assertion of status_1 is not latched and cannot be cleared by getreg command. when b7 of temperature_zone register asserts to 1 (when tsena voltage rises above 1.845v), the vrhot signal will be asserted to low. the vrhot assertion will be de- asserted when b6 of temperature_zone register is de- asserted from 1 to 0 (which means tsena voltage falls under 1.79v). the thermal monitoring function of the axg vr can be disabled by connecting tsena to vcc5. if tsena is disabled, all the svid commands related to tmperature_zone register of the axg vr will be rejected. tsena vcc5 r3 r1 r ntc r2 = load droop imona imona imonfba ir r v r (52) where i load is the output load current, r droop is the equivalent load line resistance, and r imona and r imonfba are the current monitor current setting resistors. in vr12/ imvp7 specification, the voltage signal of current monitoring will be restricted by a maximum value. platform designers have to select r imona to meet the maximum
RT8876A 45 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? = = ? qrseta on, qr on 12 ton qrseta in dac, axg v tt 1.2 20.33 10 r v vv (54) = imona(max) imona imonfba max droop v r rir (53) figure 25. axg vr : current monitoring circuit where v imona(max) is the maximum voltage at full load, and i max is the full load current of vr. after generating a quick response pulse, the pulse is then applied to the on-time generation circuit and the axg vr's on-time will be overridden by the quick response pulse. over current protection the axg vr compares a programmable current limit set point to the voltage from the current sense amplifier output for over current protection (ocp). therefore, the ocp mechanism of the RT8876A implements per-phase current protection. the voltage applied to the ocseta pin defines the desired current limit threshold i limit_axg : v ocseta = 48 x i limit_axg x r sense (55) current mirror imonfba + - r imonfba v ccaxg_sense r imona imona i mirror fba voltage of imona at full load. find r imona and r imonfba based on : the adc circuit of the axg vr monitors the voltage variation at the imona pin from 0v to 3.3v, and this voltage is decoded into digital format and stored into the output_current register. the adc divides 3.3v into 255 levels, so lsb = 3.3v/255 = 12.941mv. platform designers should design v imona to be 3.3v at iccmaxa. for example, when load current = 50% x iccmaxa, v imona = 1.65v and output_current register = 7fh. the imona pin is an output of the internal operational amplifier and sends out imona signal. when the data of output_current register reaches 255d (when imona voltage rises above 3.3v), the alert signal will be asserted to low, which is so-called svid iccmaxa alert. in the mean time, the axg vr will assert the bit 2 data to 1 in status_1 register. the alert assertion will be de- asserted when the data of output_current register decreases to 242d (when imona voltage falls under 3.144v). the bit 2 assertion of status_1 register is latched and can only be cleared when two criteria are met : the data of output_current register decreases to 242d (when imona voltage falls under 3.144v) and the getreg command is sent to the status_1 register of the axg vr. quick response the axg vr utilizes a quick response feature to support heavy load current demand during instantaneous load transient. the axg vr monitors the current of the imonfba pin, and this current is mirrored to internal quick response circuit. at steady state, this mirrored current will not trigger a quick response. when the v out, axg voltage drops abruptly due to load apply transient, the mirrored current into quick response circuit will also increase instantaneously. when the mirrored current instantaneously rises above 5 a, quick response will be triggered. when quick response is triggered, the quick response circuit will generate a quick response pulse. the internal quick response pulse generation circuit is similar to the on-time generation circuit. the only difference is the qrseta pin. the voltage at the qrseta pin also influences the pulse width of quick response. a voltage divider circuit is recommended to be applied to the qrseta pin. therefore, with a little modification of equation (45), the pulse width of quick response pulse can be calculated as :
RT8876A 46 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. solving (62) and (63) yields r oc1b and r oc2 (60) = ? + ? ? oc2 equ, hot equ, cold equ, 25 c cc5 ocseta, 25 c r rr (1)r v (1 ) v = ++ ocseta, 25 c oc2 cc5 oc1a ntc, 25 c oc1b oc2 v r v r // r r r (59) ?? = ? ?? ?? cc5 oc1 oc2 ocset v rr 1 v figure 26. axg vr : ocp setting without temperature compensation figure 27. axg vr : ocp setting with temperature compensation ocseta, hot sense, hot ocseta, cold sense, cold vr vr = (56) oc1a ntc, cold oc1b oc2 sense, hot oc1a ntc, hot oc1b oc2 sense, cold r//r r r r r//r r r r ++ = ++ (58) (57) = ++ ocseta, t c oc2 cc5 oc1a ntc, 25 c oc1b oc2 v r v r // r r r according to the basic circuit calculation, we can get v ocseta at any temperature : re-write (56) from (57) to get v o cseta at room temperature: v cc5 ocseta r oc1 r oc2 the current limit is triggered when inductor current exceeds the current limit threshold, i limit_axg , as defined by v ocseta . the driver will then be forced to turn off ugate until the condition is cleared. if the over current condition of any phase remains valid for 15 cycles, the axg vr will trigger ocp latch. latched ocp forces pwm into high impedance, which disables internal pwm logic drivers. if the over current condition is not valid for 15 continuous cycles, the ocp latch counter will be reset. when ocp is triggered by the axg vr, the core vr will also enter soft shut down sequence. if inductor dcr is used as the current sense component, temperature compensation is recommended for proper protection under all conditions. figure 26 shows a typical ocp setting with temperature compensation. ocseta v cc5 r oc1a ntc r oc1b r oc2 usually, r oc1a is selected to be equal to the thermistor's nominal resistance at room temperature. ideally, assume v ocset has the same temperature coefficient as r sense (inductor dcr) : (61) oc1b oc2 equ, hot equ, cold r (1)r r r (1 ) = ? + ? ? where sense, hot 25 c hot sense, cold 25 c cold r dcr [1 0.00393 (t 25)] r dcr [1 0.00393 (t 25)] = + ? = + ? (62) r equ, t c = r oc1a // r ntc, t c (63) over voltage protection (ovp) the over voltage protection circuit of the axg vr monitors the output voltage via the isenan pin after por. the supported maximum operating vid of the vr (v (max) ) is stored in the vout_max register. once v isenan exceeds ? v (max) + 150mv ? , ovp is triggered and latched. the axg vr will try to turn on low side mosfets and turn off connect a resistive voltage divider from vcc5 to gnd, and the joint of the resistive voltage divider is connected to the ocseta pin as shown in figure 26. for a given r oc2 ,
RT8876A 47 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. (64) ? = in out min on ripple(max) vv lt i high side mosfets of the axg vr to protect the cpu. when ovp is triggered by the axg vr, the core vr will also enter shut down sequence. a 1 s delay is used in ovp detection circuit to prevent false trigger. note that if ofsa pin is higher than 0.9v before power up, ovp would trigger when ? v (max) + 850mv ? . negative voltage protection (nvp) during ovp latch state, the axg vr also monitors the isenan pin for negative voltage protection. since the ovp latch continuously turns on all low side mosfets of the axg vr, the axg vr may suffer negative output voltage. as a consequence, when the isenan voltage drops below ? 0.05v after triggering ovp, the axg vr will trigger nvp to turn off all low side mosfets of the axg vr while the high side mosfets remains off. after triggering nvp, if the output voltage rises above 0v, the ovp latch will restart to turn on all low side mosfets. therefore, the output voltage may bounce between 0v and ? 0.05v due to ovp latch and nvp triggering. the nvp function will be active only after ovp is triggered. a 1 s delay is used in nvp detection circuit to prevent false trigger. under voltage protection (uvp) the axg vr implements under voltage protection of v out, axg , if v fba is less than the internal reference by 300mv, the axg vr will trigger uvp latch. the uvp latch will turn off both high side and low side mosfets. when uvp is triggered by the axg vr, the core vr will also enter soft shut down sequence. a 3 s delay is used in uvp detection circuit to prevent false trigger. if platform ofsa function is enabled (ofsa pin not connected to gnd), the uvp function will be disabled. under voltage lock out (uvlo) during normal operation, if the voltage at the vcc5 or vcc12 pin drops below por threshold, the axg vr will trigger uvlo. the uvlo protection forces all high side mosfets and low side mosfets off by shutting down internal pwm logic driver. a 3 s delay is used in uvlo detection circuit to prevent false trigger. where t on is the ugate turn-on period. higher inductance yields in less ripple current and hence higher efficiency. the downside is a slower transient response of the power stage to load transients. this might increase the need for more output capacitors, thus driving up the cost. select a low loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must be large enough not to be saturated at the peak inductor current. output capacitor selection output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. usually, the cpu manufacturer recommends a capacitor configuration. two different kinds of output capacitors are typically used : bulk capacitors closely located next to the inductors, and ceramic output capacitors in close proximity to the load. latter ones are for mid-frequency decoupling with especially small esr and esl values, while the bulk capacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the cpu. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja output lc filter inductor selection the switching frequency and ripple current determine the inductor value as follows :
RT8876A 48 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 26. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layers pcb where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-56l 7x7 package, the thermal resistance, ja , is 31 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (31 c/w) = 3.226w for wqfn-56l 7x7 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 26 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout considerations careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another. follow these guidelines for pc board layout considerations : ` input ceramic capacitors must be placed to the drain of high side fet and source of low side fet as close as possible. the loop (the drain of high side fet to phase node to the source of low side fet) is very critical due to it is the main emi source in buck converter, so the loop has to be minimized. ` keep the high current paths short, especially at the ground terminals. ` keep the power traces and load connections short. this is essential for high efficiency. ` when trade-offs in trace lengths must be made, it's preferable to let the inductor charging path be longer than the discharging path. ` place the current sense component close to the controller. isenxp and isenxn connections for current limit and voltage positioning must be made using kelvin sense connections to guarantee current sense accuracy. ` the pcb trace from the sense nodes should be paralleled back to the controller. ` route high speed switching nodes away from sensitive analog areas (comp, fb, isenxp, isenxn, etc...)
RT8876A 49 ds8876a-02 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 6.900 7.100 0.272 0.280 d2 5.150 5.250 0.203 0.207 e 6.900 7.100 0.272 0.280 e2 5.150 5.250 0.203 0.207 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 56l qfn 7x7 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options
RT8876A 50 ds8876a-02 october 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries.

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